The present invention relates to a semiconductor device having a multilevel interconnection structure and a method for fabricating the same.
Recent amazing progress in semiconductor processing technologies enabled super-miniaturization and a very high degree of integration of lines and devices. As a result, the performance of a ULSI has also been enhanced by leaps and bounds. However, the larger the number of lines integrated is, the more dependent the speed of a device is on the delay of a signal transmitted through the lines. In order to reduce such a delay as much as possible, various materials with lower relative dielectric constants such as fluorine-doped SiOF (the relative dielectric constant .di-elect cons. is about 3.5; that of fluorine is relatively low) and SiO:C containing an organic material (.di-elect cons. is in the range from 2.8 to 3.2) are now replacing conventionally used SiO.sub.2 (.di-elect cons. is 4.3) as materials for an interlevel dielectric film of a ULSI. These materials, however, have problems in terms of hygroscopicity and thermal resistance. Accordingly, it is difficult to effectively organize a process by using these materials.
In addition, in order to reduce a line-to-line delay particularly affecting the speed of a device, a technique for decreasing a relative dielectric constant between lines by intentionally providing an air gap, filled with the air (.di-elect cons. is 1.0), for a dielectric between the lines was also proposed (see Japanese Laid-Open Publication No. 62-5643). Hereinafter, this technique will be described with reference to FIG. 17. FIG. 17 is a cross-sectional view illustrating the structure of a conventional semiconductor device. As shown in FIG. 17, air gaps 6 and 7 are respectively provided between lines 3 and 4 and between lines 4 and 5 for a dielectric 2 on a semiconductor substrate 1 of the semiconductor device. The dielectric 2 is SiO.sub.2, for example. The capacitance between the lines 3 and 4 can be regarded as the serial connection of the capacitance between the line 3 and the air gap 6, the capacitance of the air gap 6 itself, and the capacitance between the air gap 6 and the line 4. The relative dielectric constant of the air gaps 6 and 7 filled with the air is about one-fourth as large as that of SiO.sub.2 as the dielectric 2. In this manner, the capacitance between adjacent lines can be reduced by providing air gaps and therefore the delay of a signal can be suppressed between the adjacent lines. As a result, a semiconductor device, which has a larger operating margin and is less likely to operate erroneously, is realized. In addition, since no new material needs to be used, the process can be carried out with lower costs.
In the conventional structure, however, lines and interlevel contact holes are designed in a "borderless" manner, i.e., such that the width of a line is equal to the diameter of an interlevel contact hole. Accordingly, if misalignment is caused during a photolithography process, the following problems are created. First, in opening an interlevel contact hole, the interlevel contact hole is adversely joined with an associated air gap. Since an interconnecting metal, filled in the interlevel contact hole, enters the joined region, a shortcircuit failure is generated in the line. Second, since the contact area between the interconnecting metal, filled in the interlevel contact hole, and the line is smaller, a contact failure is more likely to happen.
These failures will be described with reference to FIGS. 18A through 18E illustrating the flow of a conventional process for fabricating a multilevel interconnection structure of a semiconductor device. First, as shown in FIG. 18A, an insulating film 12, a first interconnect layer 13 and an interlevel dielectric film 14 are formed in this order over a semiconductor substrate 11. In this case, since an SiO.sub.2 film is deposited as the interlevel dielectric film 14 by a plasma CVD technique, the step coverage is poor. That is to say, the ratio of the thickness of the deposited film at a line-to-line space 15 in the first interconnect layer 13 to the thickness thereof in the planar region is low. As a result, an air gap 16 is formed at the line-to-line space 15 in the interlevel dielectric film 14. However, since the step coverage does not become 0%, the air gap does not completely occupy the line-to-line space 15 and the interlevel dielectric film 14 partially exists between the lines. Accordingly, in order to reduce the relative dielectric constant between the lines, the deposition rate of the interlevel dielectric film 14 may be further decreased at the line-to-line space 15. In such a case, the air gap 16 occupies an even larger region. Next, as shown in FIG. 18B, the interlevel dielectric film 14 is partially removed by a resist etchback technique, a chemical/mechanical polishing (CMP) technique or the like to planarize the surface of the interlevel dielectric film 14.
Then, as shown in FIG. 18C, an interlevel contact hole 17 is formed by photolithography and dry etching techniques. Assume that the width 18 of a line in the first interconnect layer 13 is equal to the diameter 19 of the interlevel contact hole 17, and that misalignment was caused during the photolithography to shift the right edge of the contact hole 17 leftward by an alignment error 20. In such a case, as a result of the misalignment, part of the interlevel contact hole 17 is joined with the air gap 16 to reach a deeper level than the upper surface of the first interconnect layer 13 in the region that has shifted leftward.
Subsequently, as shown in FIG. 18D, the interlevel contact hole 17 is filled in with an interconnecting metal 21 such as tungsten in accordance with a CVD technique. If tungsten 21 is filled in by a CVD technique in this manner, then satisfactory step coverage can be attained. Accordingly, not only the interlevel contact hole 17 shown in FIG. 18C but also the air gap 16 are filled in with tungsten 21. As a result, a shortcircuit failure is generated, because adjacent lines in the first interconnect layer 13 are unintentionally connected to each other via the interconnecting metal 21 filled in a part that used to be the air gap 16. In accordance with this method, if the relative dielectric constant in the line-to-line space 15 is reduced, then the air gap 16 occupies an even larger region. As a result, the shortcircuit failure is even more likely to happen. On the other hand, the larger the misaligned error 20 shown in FIG. 18C is, the smaller the contact area between the line in the first interconnect layer 13 and the interconnecting metal 21, filled in the interlevel contact hole 17, is. Consequently, a contact failure is caused between the line and the interconnecting metal 21. Particularly when an organic material is used for the interlevel dielectric film 14, the contact failure is much more likely to happen. Furthermore, if a deeper interlevel contact hole 17 has been formed by etching, a shortcircuit failure is generated, because a line in the first interconnect layer 13 is unintentionally connected to the semiconductor substrate 11 through the interconnecting metal 21. Thereafter, as shown in FIG. 18E, a second interconnect layer 22 is formed on the interconnecting metal 21 and the interlevel dielectric film 14 so as to be interconnected to the first interconnect layer 13 though the interconnecting metal 21.